TMA: Tera‐MACs/W neural hardware inference accelerator with a multiplier‐less massive parallel processor

Computationally intensive inference tasks of deep neural networks have brought about a revolution in accelerator architecture, aiming to reduce power consumption as well latency. The key figure-of-merit hardware accelerators is the number multiply-and-accumulation operations per watt (MACs/W); state-of- the-art MACs/W, so far, has been several hundreds Giga-MACs/W. We propose Tera- MACS/W (TMA) with 8-bit activations and scalable integer weights less than 1-byte. architecture's main feature configurable processing element for matrix-vector operations. proposed uses multiplier-less massive parallel processor that works without multipliers, which makes it attractive energy efficient high-performance network applications. benchmark our system's latency, power, performance using Alexnet trained on ImageNet. Finally, we compared accelerator's throughput prior works. outperforms state-of-the-art counterparts, terms area efficiency, achieving 2.3 TMACs/[email protected] V 28-nm Virtex-7 FPGA chip.